The present invention relates to a converter, and particularly, to a DC-DC converter and a control circuit for a DC-DC converter.
FIG. 1 is a schematic circuit diagram showing a current-mode DC-DC converter 1. The DC-DC converter 1 includes a control unit 2 and a converter unit. The converter unit includes an output transistor T1 configured by an N-channel MOS transistor, a synchronous rectifying transistor T2 configured by an N-channel MOS transistor, a Zener diode D1, a choke coil L1, a current detection resistor Rs, and a smoothing capacitor C1.
The control unit 2 generates complementary control signals DH and DL and provides the control signal DH to the gate of the output transistor T1 and the control signal DL to the gate of the synchronous rectifying transistor T2.
An input voltage Vi is supplied to the drain of the output transistor T1. When the control signal DH rises to H level, the output transistor T1 is activated and an output voltage Vo is generated at an output terminal via the choke coil L1 and the current detection resistor Rs. Upon the rising of the control signal DL to H level, the synchronous rectifying transistor T2 is activated, and the output voltage Vo is generated by the energy stored in the choke coil L1. The output voltage Vo is smoothed by the smoothing capacitor C1.
The control unit 2 receives the input voltage Vi as a power supply Vcc. The control unit 2 has a voltage amplifier 3 which receives voltage between the two terminals of the current detection resistor Rs, amplifies the voltage based on output current that is proportional to the voltage and flows through the current detection resistor Rs, and provides the amplified signal to the comparator 4.
The control unit 2 has an error amplifier 5, which amplifies a differential voltage between a voltage obtained by dividing the output voltage Vo by the resistors R1 and R2 and the output voltage of a reference power supply e1, and provides the amplified signal to the comparator 4. The voltage of the reference power supply e1 is set to be equal to the divided voltages of the resistor R1 and R2 when the output voltage Vo reaches a regulated value.
The comparator 4 compares the voltage of the amplified signal of the voltage amplifier 3 with the voltage of the amplified signal of the error amplifier 5. If the voltage of the amplified signal of the voltage amplifier 3 is higher than the voltage of the amplified signal of the error amplifier 5, the comparator 4 provides an H-level output signal to a reset terminal R of a flip-flop circuit (hereafter referred to as the “FF circuit”) 7. If the voltage of the amplified signal of the voltage amplifier 3 is lower than the voltage of the amplified signal of the error amplifier 5, the comparator 4 provides an L-level output signal to the reset terminal R.
The FF circuit 7 has a set terminal S to which a pulse signal having a fixed frequency is provided from an oscillator 6. When an H-level pulse signal is applied to the set terminal S, the FF circuit 7 generates an H-level control signal DH at its output terminal Q, while generating an L-level control signal DL at its inverting output terminal /Q. When an H-level output signal is applied to the reset terminal R, the FF circuit 7 generates an L-level control signal DH and an H-level control signal DL.
The control unit 2 activates the output transistor T1 in fixed cycles in response to the rising of the pulse signal of the oscillator 6. When the output transistor T1 is activated, the current IL flowing through the choke coil L1 and the current detection resistor Rs is increased. This raises the voltage of a first amplified signal of the voltage amplifier 3. When the voltage of the amplified signal of the voltage amplifier 3 becomes higher than the voltage of the amplified signal of the error amplifier 5, an H-level output signal is provided to the reset terminal R of the FF circuit 7. The output transistor T1 is thereby inactivated and the synchronous rectifying transistor T2 is activated. As a result, the energy stored in the choke coil L1 is output.
If the output voltage Vo decreases during the activation and inactivation of the output transistor, the voltage of the amplified signal of the error amplifier 5 becomes higher than the voltage of the amplified signal of the voltage amplifier 3. The output signal of the comparator 4 then rises to an H level after a relatively long period of time. This lengthens the time for the output transistor T1 to be activated. If the output voltage Vo increases, the voltage of the amplified signal of the error amplifier 5 becomes lower than the voltage of the amplified signal of the voltage amplifier 3. The output signal of the comparator 4 then rises to H level after a relative short period of time. This shortens the time for the output transistor T1 to be activated. The output transistor T1 is thus activated repeatedly at fixed periods in response to the output signal frequency of the oscillator 6. The inactivation timing of the output transistor T1 is determined according to the increase rate of the output current IL. The inactivation timing of the output transistor T1 is thus changed in response to the increase and decrease of the output voltage Vo. This keeps the output voltage Vo constant.
In the current-mode DC-DC converter, when the ON duty (Ton/(Ton+Toff)) becomes higher than 50%, the increase rate (inclination of increase) of the current IL flowing through the choke coil L1 decreases. Thus, the change in the output signal (voltage increase rate) of the voltage amplifier 3 becomes moderate. Ton denotes the time during which the output transistor T1 is active, and Toff denotes the time during which the output transistor T1 is inactive. If the amplified signal of the voltage amplifier 3 includes noise, the noise will cause delay in the shifting of the signal of the comparator 4 (the timing of generating an H-level output signal will be offset). That is, the timing for providing an H-level output signal to the reset terminal R of the FF circuit 7 is delayed. An H-level signal is cyclically provided to the set terminal S of the FF circuit 7 from the oscillator 6. Therefore, the set terminal may be provided with an H-level pulse signal earlier than when the reset terminal R is provided with an H-level output signal. In such a case, the FF circuit 7 remains set thereby lengthening the set time. This state is equivalent to a state in which the FF circuit 7 is set by a signal with a lower frequency than the oscillatory frequency of the oscillator 6. This is referred to as low harmonic oscillation. In other words, erroneous circuit functioning caused by noise may cause low harmonic oscillation. As shown in FIG. 3, the output current IL increases when such low harmonic oscillation occurs. This increases the output voltage Vo. For this reason, the occurrence of low harmonic oscillation destabilizes the output voltage Vo.
FIG. 2 shows an example of a known DC-DC converter that prevents low harmonic oscillation caused by erroneous circuit functioning due to noise. This DC-DC converter has a slope compensation control function, which superimposes a correction voltage on a signal having a voltage corresponding to current IL flowing through a choke coil L1 (amplified signal of a voltage amplifier 3) with a slope compensation circuit 8 (e.g. variable power supply) to increase the voltage increase rate of the amplified signal. This function reduces signal shifting delays in the comparator 4 and prevents the occurrence of low harmonic oscillation even if noise is included in the amplified signal.